The invention lies in the field of communications. The present invention relates to an apparatus and a method for filtering a plurality of data trains by time division multiplexing.
There are many applications in which two or more digital data streams or trains have to be filtered in the same way. In television technology, for instance, it may be necessary for data triplets, such as trains of RGB or YUV data to be decimated by the same factor.
In multiplex transmission of a plurality of data trains over a common channel, it can also become necessary to adapt the bandwidth of the data trains to the transmission bandwidth of the channel by low-pass filtering that is uniform for all the trains. The maximum frequency present in each data train must not be any higher than xc2xdn times the scanning frequency or the transmission frequency of the channel. Otherwise, problems known as aliases occur.
To keep these problems as slight as possible, it is typical to low-pass filter the data trains individually before their transmission over the channel. After the filtration, a new train is formed from the plurality of data trains with the aid of a reversing switch; the new train is composed cyclically of values from the different starting trains and can be transmitted over the channel.
The low-pass filters used for such purpose have transfer functions of the following form, for example
H(zxe2x88x921)=(1xe2x88x92zxe2x88x921)m
and include a series circuit of register-adder units, in which the inputs of the adders are each connected once directly and once through a delay register to the input of the unit.
These conventional filters, because of their construction, determine one output value for each input value of an original train. It is possible that because of a limited transmission capacity of the transmission channel, only some of these values can be picked up; this means that the others were determined in vain.
It is accordingly an object of the invention to provide an apparatus and a method for filtering a plurality of data trains by time division multiplexing that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that make it possible to reduce the expense for circuitry involved in reserving a separate filter for each original data train, and thus to minimize the substrate area required for integrating such filters.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a filter for filtering n data trains by time division multiplexing, in which n is an integer greater than 1, including data channels for receiving values of the n data trains, registers for buffer storage of at least one of the values of the n data trains and derived values derived from the n data trains, the registers subdivided into n groups, each of the n groups of the registers connected to at least one of the data channels for receiving the values of the n data trains, and adders each having a first input and a second input, the adders and the registers alternatively connected to one another to form a chain, the first input of each respective adder connected upstream of a respective one of the registers of an ith group (0xe2x89xa6ixe2x89xa6nxe2x88x921) of the n groups has a connection to a respective one of the data channels assigned to the ith group of the n groups, and the second input of a corresponding respective adder connected to a respective one of the registers of a group having a number (ixe2x88x921)mod n without an intervening register of another of the groups.
The structure of the filter makes it possible to process a plurality of data trains simultaneously in one and the same filter, and, at every instant, the registers of one group contain only values that are derived from the values of a single one of the original trains.
Each time the registers of the filter are activated in order to store the values applied to their input, these values move onward only to the next group, without being affected by the values of other trains.
In accordance with another feature of the invention, there is provided a multiplier disposed between each of the n groups and at least one of the data channels.
In accordance with a further feature of the invention, there are provided parallel multipliers for multiplication by various factors, the parallel multipliers disposed between each of the n groups and at least one of the data channels, and a switch for selectively connecting one of the multipliers with a respective one of the adders.
In accordance with an added feature of the invention, there is provided at least one multiplier for multiplication by a factor k not a power of two, the at least one multiplier disposed between each of the n groups and at least one of the data channels and having parallel submultipliers for multiplying by a power of two (2j), the parallel submultipliers having input data lines and output lines, the parallel submultipliers having a connection of the input data lines to the output lines each left-shifted by j bits, and further adders connected to the parallel submultipliers adding output values of the parallel submultipliers.
In accordance with an additional feature of the invention, the chain has m adders of the adders with an output and m registers of the registers with an input, an input of a 0th register of the registers is connected to a respective data channel, and an input of a jth register is connected to an output of a (jxe2x88x921)th adder for all j greater than 0, the chain realizing a transfer function (H(zxe2x88x921)=xcexa3ajzxe2x88x92j) represented as a polynomial in zxe2x88x921 where j=0, 1, . . . , mxe2x88x921.
The filter according to the invention with a polynomial transfer function H(zxe2x88x921)=xcexa3ajzxe2x88x92j can be constructed as a series circuit of m register-adder units; the first input of the 0th unit is connected to the associated signal channel, and the first inputs of all the other units are each connected to the output of the unit immediately preceding each of them.
In accordance with yet another feature of the invention, there is provided a multiplier, the m adders having an input, and the input of a jth adder of the m adders being connected to a respective data channel through the multiplier for multiplication by the factor aj for all ajxe2x89xa01.
A filter according to the invention is simple to construct by providing, for all factors ajxe2x89xa01 of the transfer function, one multiplier for multiplication by the factor aj, which connects the second input of the jth unit to the assigned data channel.
Multipliers for multiplication by a power of two 2j can be formed in a very simple way by a submultiplier that contains only a single data line, whose bit inputs are each linked with outputs whose value is higher by j bits.
Multipliers for multiplication by an arbitrary factor can be constructed from a plurality of submultipliers, in accordance with the powers of two contained in the factor, and adders for adding the outputs of the submultipliers.
In accordance with yet a further feature of the invention, at least one of the n groups has two registers of the registers each with an output, and at least one adder of the adders has two inputs respectively connected to the output of the two registers.
In accordance with yet an added feature of the invention, there is provided a switch, the registers each having an output, and the switch connecting an output of a register of a group (i+1)mod n(0xe2x89xa6ixe2x89xa6nxe2x88x921) of the registers selectively to at least one of the first input and the second input of respective adders connected upstream of respective registers of the registers of a group i of the n groups.
In accordance with yet an additional feature of the invention, there is provided a switch, the registers each having an output, and the switch connecting an input of a respective adder of the adders connected upstream of a register of a group (i+1)mod n(0xe2x89xa6ixe2x89xa6nxe2x88x921) of the n groups selectively to an output of respective registers of the registers of a group i of the n groups.
In accordance with again another feature of the invention, there is provided a multiplexer having n inputs for each of the n data trains and n outputs, each of the n outputs respectively connected to one of the data channels, the multiplexer outputting data values of one of the n data trains in cyclic alternation to the data channels.
Expediently, the filter also includes a multiplexer with n inputs for the n inputs and n outputs, to each of which one of the n signal channels is connected. The multiplexer is configured to output data values of one of the data trains in cyclic alternation to the various data channels.
In accordance with again a further feature of the invention, there is provided a demultiplexer having outputs, each of the outputs forming one output connected to a respective one of the n data trains of the filter, one of the adders having an output, and the demultiplexer connected to the output of the one of the adders.
For sorting out filtered values derived from various different data trains, a demultiplexer can be provided as an output stage of the filter optionally downstream of the transmission route. The demultiplexer is connected to the output of one of the units and has n outputs, each of the n outputs forms one output assigned to one of the data trains of the filter.
With the objects of the invention in view, there is also provided a filter configuration, including a filter for filtering two data trains by time division multiplexing having data channels for receiving values of the two data trains, registers for buffer storage of at least one of the values of the two data trains and derived values derived from the two data trains, the registers subdivided into n groups, each of the n groups of the registers connected to at least one of the data channels for receiving the values of the two data trains, and adders each having a first input and a second input, the adders and the registers alternatively connected to one another to form a chain, the first input of each respective adder connected upstream of a respective one of the registers of an ith group (0xe2x89xa6ixe2x89xa6nxe2x88x921) of the n groups has a connection to a respective one of the data channels assigned to the ith group of the n groups, and the second input of a corresponding respective adder connected to a respective one of the registers of a group having the number (ixe2x88x921)mod n without an intervening register of another of the groups, and two multipliers receiving values of a common original train, alternatively multiplying received values with sine factors and cosine factors, and outputting correspondingly multiplied values to the data channels to generate two quadrature modulated data trains from the original train.
With the objects of the invention in view, there is also provided a method for operating a filter for filtering n data trains by time division multiplexing, in which n is an integer greater than 1, including receiving values of the n data trains through data channels, buffer storing at least one of values of the n data trains and derived values derived from the n data trains with registers and subdividing the registers into n groups, alternatively connecting adders and the registers to one another to form a chain, each of the adders having first and second inputs, connecting each of the n groups to at least one of the data channels, connecting a respective adder upstream of a respective one of the registers of an ith group (0xe2x89xa6ixe2x89xa6nxe2x88x921) of the groups, and connecting the first input of each respective adder to a respective one of the data channels assigned to the ith group of the n groups, connecting the second input of a corresponding respective adder to a respective one of the registers of a group having a number (ixe2x88x921)mod n without an intervening register of another of the n groups, applying a value of the ith data train to the data channel of the group (i+d)mod n for all i=0, . . . , nxe2x88x921, storing in each respective register the values present at the first inputs of each respective register, varying d in the applying step by 1, and repeating, at least once, the applying step, the storing step, and the varying step.
In accordance with again an added mode of the invention, the n data trains each have a clock rate, and setting clock rates of all of the n data trains to be the same.
In accordance with again an additional mode of the invention, the n data trains each have a clock period, and performing the applying step, the storing step, the varying step, and the repeating step n times during each clock period of the n data trains.
The output data rate of the filter can be selected largely freely in adaptation to the transmission capacity of the transmission channel. If the method steps are performed n times in each clock period of the original data trains, then for each input original data value, one filtered value is generated. If the steps are performed only once per clock period, this corresponds to a decimation of the original data by the factor n. In each case, regardless of the number of repetitions, however, with the filter of the invention no more data values than are actually output over the transmission channel are generated. Thus, the invention avoids the excess computation expense involved in conventional filters that decimate the data before the data is transmitted.
In accordance with still another mode of the invention, the n data trains each have a clock period, and performing the applying step, the storing step, the varying step, and the repeating step once during each clock period of the n data trains.
With the objects of the invention in view, there is also provided a method for operating a filter for filtering n data trains by time division multiplexing, in which n is an integer greater than 1, including providing a filter having data channels for receiving values of the n data trains, registers for buffer storage of at least one of the values of the n data trains and derived values derived from the n data trains, the registers subdivided into n groups, each of the n groups connected to at least one of the data channels for receiving values of the n data trains, and adders each having first and second inputs, the adders and the registers alternatively connected to one another to form a chain, the first input of each respective adder connected upstream of a respective one of the registers of an ith group (0xe2x89xa6ixe2x89xa6nxe2x88x921) of the n groups has a connection to a respective one of the data channels assigned to the ith group of the n groups, and the second input of a corresponding respective adder connected to a respective one of the registers of a group having the number (ixe2x88x921)mod n without an intervening register of another of the n groups, and parallelly decimating the n data trains by a common factor using the filter.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a filter for time division multiplex filtering of a plurality of data trains, and operating methods therefor, it is nevertheless not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.